1. Field of the Invention
The present invention relates to a data output buffer of a semiconductor device and, more particularly, to a duty cycle adaptive data output buffer in which current driving power of an output buffer is adaptively varied with a duty cycle, to effectively improve. its noise margin at slow duty cycle.
2. Description of Related Art
A synchronous dynamic random access memory (SDRAM) which operates in synchronization with a system clock signal SC generally has an access time and duty cycle (for example, cycle frequency of system clock signal SC: 66 MHz, 100 MHz, 120 MHz, 150 MHz, . . . ) faster than those of a conventional DRAM. To achieve a faster duty cycle and access time, a conventional data output buffer is constructed in such a manner that the last output driver for driving an external capacitive load of a semiconductor device chip has a large channel width (for example, channel width is 500 .mu.m or more), to make the edge slope of the last data output steeply inclined.
FIG. 1 shows the data output buffer of a conventional semiconductor device. Referring to FIG. 1, a pull-up driver 10 connected between a power supply voltage VDD and an output terminal Dout, and a pull-down driver 9 connected between the output terminal Dout and a ground VSS include NMOS transistors N1 and N2 respectively. The pull-up driver 10 and the pull-down driver 9 are driven by using data signals D and DB internally sensed in the chip through NAND gates NA1 and NA2 and inverters INV3 and INV4, in response to an output enable signal .phi.TRST. The Data signals D and DB internally sensed in the chip are applied to the gates of transistors N1 and N2 when the output enable signal .phi.TRST is in HIGH state, so as to be output from the output terminal Dout according to the operation of the pull-up and pull-down drivers 10 and 9.
In the above-described conventional data output buffer, for the purpose of covering low-frequency and high-frequency operation regions to satisfy a target operation speed required when the output buffer is operated at high frequency, the size of the drivers is fixed to the size of the pull-up and pull-down drivers for high frequency. Accordingly, the size of the output drivers will support the highest frequency so that the channel width of the NMOS transistors N1 and N2 may be fixed.
With the conventional data output buffer, the output driver is operated fast when the data output buffer is operated at lower frequency. However, due to large-size NMOS transistors N1 and N2, a large amount of current is transmitted through the power supply voltage VDD and the ground voltage VSS in a short period time according to fast slope (or transition) of the data output signal Dout when the data output signal Dout is output. This causes overshooting or undershooting of the power supply voltage VDD and the ground voltage VSS. The overshooting and undershooting affect the DC noise margin in the chip. This problem is also generated when the output buffer is operated at higher frequency. Accordingly, in the conventional data output buffer, when the size of the transistor is large in order to meet the high-speed operation, the power noise margin is strictly restricted when the data output buffer is operated at slower speed.